1. Field of the Invention
The present invention relates to the fabrication of semiconductor integrated circuits (IC's). More particularly, the present invention relates to improved methods and systems for etching dielectric layers of semiconductor devices with reduced damage to transistor device gate oxides.
2. Description of the Related Art
In semiconductor IC fabrication, devices such as component transistors are formed on a semiconductor wafer substrate, which is typically made of silicon. During the fabrication process, various materials are deposited on different layers in order to build a desired IC. Typically, conductive layers, which may include patterned metallization lines, polysilicon transistor gates and the like, are insulated from one another by dielectric material layers. Such dielectric layers typically include thermally grown silicon dioxide (SiO.sub.2), tetra-ethyl-ortho-silicate (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), USG (undoped spin-on-glass), LTO, etc. Because semiconductor ICs are fabricated as multi-layered structures, there is a common need to interconnect IC features that are patterned on one layer to IC features of other layers. To accomplish these interconnections, via holes are typically etched through the dielectric materials down to underlying features.
Once the via holes are etched, the via holes are filled with a conductive material (e.g., tungsten, aluminum, etc.) to establish conductive vias between features of the underlayer and a subsequently deposited and patterned metallization layer. In other cases, via holes are etched down to an underlying polysilicon transistor gate or silicon wafer diffusion region. Once these vias are etched, the via holes are conductively filled to form electrical "contacts" between the underlying devices and a subsequently deposited and patterned metallization layer.
FIG. 1 is a cross-sectional view of a partially fabricated semiconductor device 100. As shown, a semiconductor substrate 102 has exemplary diffusion regions 104, a gate oxide 110, and a polysilicon gate 112, which define a transistor device. As mentioned above, a dielectric material 106 is commonly formed over the transistor devices to insulate them from subsequently deposited and patterned metallization lines (not shown). As device features continue to be designed smaller and smaller, vias etched through the dielectric material 106 will have higher aspect ratios (i.e., deeper and narrower vias). To facilitate etching of these high aspect ratio via holes, fabrication engineers have been more frequently implementing high density plasma etchers. High density plasma etchers are also now preferred over capacitively coupled source etchers due to their unique ability to provide substantially improved etch rates.
Although high density etchers have these benefits, they also have the downside of introducing a substantial amount of charge into the substrate when contact via holes are etched down to diffusion regions 104. As is well known, the plasma etch 114 operation is typically performed after a photoresist layer 108 is spin-coated over the surface of the dielectric layer 106 and then patterned using conventional photolithography techniques. In the example of FIG. 1, upon breaking through the dielectric layer 106 to a diffusion region 104, a potential difference will typically develop between the top surface of the polysilicon gate 112 (P1) and the top surface of the diffusion region 104 (P2).
FIG. 1 also shows an open area 116, which arises due to a relatively large opening in the photoresist mask 108. The open area 116 may represent the wafer edge region, in the case that photoresist edge bead removal has been employed prior to etching. The open area 116 may also represent scribe lines, or any other opening which has a width substantially greater than the dielectric film thickness. Upon breaking through the dielectric layer 106 to the open area 116, a potential difference will typically develop between the top surface of the polysilicon gate 112 (P1) and the open area 116 (P3).
A potential difference across the gate oxide 110 may also be induced in the case which is similar to that of FIG. 1, but where the contact via to the polysilicon gate 112 has already been etched and subsequently filled with a conductive material such as tungsten. In this case, the potential of the photoresist layer 108 (P4) will be roughly equal to the potential at the top surface of the polysilicon gate 112 (P1), and will differ from the potential of the top surface of the diffusion region 104 (P2) or at the top surface of the open area 116 (P3).
Due to the different geometries of the etched features, the charged particles impacting the wafer films and wafer substrate from the plasma may induce potential differences. The continuing flux of charged particles allows a substantial current "I" to develop across the potential gradients. This current I is unfortunately much greater than the level of current the gate oxide 110 was designed to handle. As a result of the plasma-induced current through the gate structure, fabrication and reliability engineers have observed a great deal of damage to the gate oxides 110 throughout transistor devices of a silicon wafer. In many cases, the potential difference across the gate oxides 110 will be so large that the oxide material will degrade to the point where the particular transistor devices will no longer work in their intended mode of operation. In other cases, the damage to the gate oxides 110 will be such that the transistor devices will fail to meet specific reliability and operational requirements.
In view of the foregoing, what is needed are methods and systems for etching vias that make electrical contact with the silicon substrate using high density plasma etchers, while reducing damage to sensitive gate oxides of transistor devices throughout the silicon substrate.